1. Field of the Invention
The present invention relates to a data recording method and a data recording apparatus for coding data by using a so-called (1,7) code and recording the data into a recording medium.
2. Related Background Art
FIG. 1 shows a coding table of the most common (1,7) code. In this code, (d,k,m,n)=(1,7,2,3), i.e., the number of "0"s present between "1"s is a minimum of one and a maximum of seven, and the conversion bit ratio is 2:3. In this table, X represents an indeterminate bit which is determined by the pattern before this bit.
FIG. 2 illustrates a sector format proposed as a standard of a rewritable 300-mm optical disk, as an example of a sector format using this (1,7) code. Referring to FIG. 2, a 67-byte portion as a header field is an area in which address information is already recorded on a disk, and a 1,293-byte portion as a recording field is an area in which new information is recorded. FIG. 3 explains in detail a 3-byte DS portion and a 1,249-byte data field portion in that area.
The data field shown in FIG. 3 contains a data sync pattern SB1-3 which indicates the start position of data, user data D1 to D1024, address data A1 and A2, CRC parities (error-detecting codes) C1 to C4, ECC parities (error-correcting codes) E1,1 to E10,14, and resync (resynchronization) patterns RS1 to RS59. These patterns, data, and parities are coded and recorded by the (1,7) code described above.
The purpose of the resync pattern is to record a predetermined pattern at a fixed period. That is, if a large omission of data takes place in a reproduction signal during reproduction, this shifts the phase of a reproduction phase locked loop (PLL) clock, making byte synchronization of reproduction information impossible. Even if this synchronization difference propagates, it is possible to perform resynchronization by detecting the resync pattern and thereby minimize the damage.
The one-byte resync pattern proposed in this standard is a pattern "X01000001000" which is obtained by converting "C5" into the (1,7) code in hexadecimal notation.
It is desirable that the resync pattern be a pattern which does not appear in user data. If the same pattern as the resync pattern appears in user data, a resync pattern detection circuit erroneously detects the resync pattern, producing a large error in reproduction data. To prevent this, windows for detecting the resync pattern can be provided in intervals before and after a point at which the resync pattern is expected to be detected, thereby making it impossible to detect the resync pattern in a data area.
FIG. 4 is a timing chart for explaining the function of such a resync detection window. Referring to FIG. 4, RS represents a true resync signal, UD represents user data, WS represents a false resync signal in the user data, and T represents a fixed time.
Assume that the window is narrowed so as not to erroneously detect the false resync pattern in the user data area. In this case, if an omission of data occurs in a reproduction signal, the resync pattern may fall outside the window due to an error in the frequency of the reproduction signal and therefore may no longer be detected. If, in contrast, the window is widened so as not to miss the true resync pattern, the false resync pattern in the user data area may be erroneously detected.
For this reason, the standard of a rewritable optical disk using a (2,7) code, for example, makes use of a pattern, which satisfies a (2,7) limitation, i.e., "0010000000100100," and does not appear in a data area written by the (2,7) code, as the resync pattern. The above-mentioned resync pattern of the (1,7) code, however, is a pattern that appears in the user data area.
A pattern indicated by "1000000010000001," therefore, which satisfies the (d,k) limitation of (1,7) is used. Such a pattern in which an 8-t period is followed by a 7-t period meets the condition (d,k)=(1,7) and does not appear in the (1,7)-code coding table mentioned earlier. The use of this pattern as the resync pattern can solve the above problem. If, however, this pattern is used, the resync pattern consists of at least two bytes. In FIG. 3, a resync pattern of one byte is added every 20 bytes of user data. The efficiency of recording capacity decreases if a resync pattern of two bytes must be added every 20 bytes of user data.
Another problem on which the present invention has focused attention is a problem of DC free of a coded signal. Assuming that symbol 1 is +1 point and symbol is -1 point in a recording waveform column, the sum of points in a given waveform column is termed a digital sum value (DSV). A code in which a DSV in a certain predetermined interval is 0 or has a finite value does not have a DC component in its waveform column and hence is called a DC free code. When this DC free code is used, a binary circuit of a reproducing apparatus can be simplified because no DC component is contained in a reproduction signal. This effectively reduces jitters produced by binary errors.
Examples of the DC free code are PE modulation, FM modulation, a Miller.sup.2 (Miller square) code, and an EFM code. These codes, however, have their respective drawbacks, such as a low recording density, a small window margin, and complexity in a coding circuit.
On the other hand, it is also possible to perform mark-edge recording for a run length limited (RLL) code, such as the (1,7) code or the (2,7) code, which is often used in mark-position recording, for the purpose of increasing the recording density. That is, as shown in FIG. 5, it is possible to convert the RLL code into a non return to zero inverted (NRZI) code, thereby using it as a (1,7) NRZI code or a (2,7) NRZI code.
There is a conventionally known method for converting these non DC free codes into DC free codes by providing a DC free control bit at a predetermined period. That is, by properly selecting the DC free control bit provided at the fixed period, a DSV value as a whole can be so controlled as not to be greater than a predetermined value.